RT Level Hardware Description with VHDL:Sequential Circuits
Sequential Circuits As with any digital circuit, a sequential circuit can be described in VHDL by the use of gates, Boolean expressions, or behavioral constructs (e.g., process statement s). Although gate level description allows a more detailed description of timing and delays, because of the complexity of clocking, and register and flip-flop controls, sequential circuits are usually described by process statement s. In the next section we will first discuss some basic elements at the gate level and then represent coding styles for more complex sequential circuits. Basic Memory Elements at the Gate Level A clocked D-latch latches its input data when clock is active. The latch structure retains its value until the next active clock cycle. This element is the basis of all static memory elements. Figure 87.19 shows a simple implementation of the D-latch that uses cross-coupled NOR gates, while the corresponding VHDL code is shown in Figure 87.20. Notice the use of buffer for q a...