RT Level Hardware Description with VHDL:Writing Testbenches

Writing Testbenches

Coding styles presented so far were for coding hardware structures, with the intention of synthesizability. On the other hand, testbenches do not need to have hardware correspondence. The VHDL code of Figure 87.31 which is a 101 Moore detector will be used as the design under test (DUT) in this section.

Figure 87.37 shows a testbench developed for the Moore detector of Figure 87.31. The testbench entity which instantiates design under test (DUT), Moore_detector in this example, has no ports. Initial values of DUT inputs are assigned in the signal declarations stated in the declarative part of this architecture. This testbench applies test data to DUT. This testbench uses three processes: one condi- tional signal assignment and two process statements. It should be kept in mind that all the processes run concurrently. The first process waits for 20 ns and then puts 0 into clr_t. It then executes a wait which suspends it forever.

Normally a process statement executes all its sequential statements and then repeats itself. However, a process may suspend itself by using a wait statement. Wait statements have several forms and can only be used in sequential blocks. Using wait without any parameter suspends the process forever, but when followed by for and a wait time, causes suspension of the process statement until this time elapses. There are other types of wait statements, such as wait on and wait until that wait on events in their sensitivity clause and until the wait condition in their condition clause becomes true, respectively.

Coming back to our test bench example, the second process is a conditional signal assignment and is responsible for producing the clk signal while the last process creates the x signal. The third process waits for a certain amount of time and then complements its variable, which generates periodic data.